Power supply system and image forming apparatus having power supply system

ABSTRACT

A power supply system includes: a switching power supply generating a voltage from an alternating current power supply; capacitors connected to the alternating current power supply; a rectification circuit configured to rectify an alternating current voltage applied to the capacitors; a backflow regulation regulating backflow of current from the switching power supply; a signal generation circuit generating a detection signal corresponding to a zero cross point of the alternating current power supply; a power supply line connected to the switching power supply and the rectification circuit; an electricity storage unit connected to the power supply line; a voltage limit element configured to limit a voltage of the output line of the rectification circuit, and a control unit, power being fed to the control unit through the power supply line. The control unit is configured to detect a zero cross point based on the detection signal.

CROSS REFERENCE TO RELATED APPLICATION

This application is based upon and claims the benefit of priority of Japanese Patent Application No. 2013-066393 filed on Mar. 27, 2013, the contents of which are incorporated herein by reference in its entirety.

BACKGROUND

The present disclosure relates to a power supply system and an image forming apparatus having the power supply system, and more particularly, to a technology of detecting a zero cross point of an alternating current voltage.

Conventionally, for example, JP-A-2010-239774 discloses a technology of detecting a zero cross point (zero cross timing) of an alternating current voltage. In the technical document, the zero cross point of the alternating current voltage is detected using a photo coupler.

SUMMARY

According to the method of detecting the zero cross point by using the photo coupler, like the above technical document, the zero cross point can be favorably detected. However, the power consumption, which is consumed by a photo diode of the photo coupler, is not negligibly low. For this reason, a technology of more saving power while maintaining detection reliability of the zero cross point is seriously needed.

The aspect of the present disclosure provides a technology of more saving power while maintaining detection reliability of a zero cross point.

one of aspects of the present disclosure provides the following arrangements:

A power supply system comprising:

a switching power supply configured to rectify and smooth an alternating current voltage of an alternating current power supply and generate a predetermined direct current voltage;

a first capacitor including a first electrode and a second electrode, the first electrode being connected to one end of the alternating current power supply;

a second capacitor including a third electrode and a fourth electrode, the third electrode being connected to the other end of the alternating current power supply;

a rectification circuit configured to rectify an alternating current voltage applied to the first and second capacitors, the rectification circuit including an output line connected with an output line of the switching power supply;

a backflow regulation element that is provided on the output line of the rectification circuit and is configured to regulate backflow of current from the switching power supply towards the rectification circuit;

a signal generation circuit connected to the output line of the rectification circuit, the signal generation circuit configured to generate a detection signal corresponding to a zero cross point of the alternating current power supply based on an output of the rectification circuit;

a power supply line positioned at a more downstream side than the backflow regulation element and connected to the output line of the switching power supply and the output line of the rectification circuit;

an electricity storage unit connected to the power supply line;

a voltage limit element configured to limit a voltage of the output line of the rectification circuit to be lower than a voltage of the power supply line, and

a control unit that is positioned at a more downstream side than the electricity storage unit, power being fed to the control unit through the power supply line,

wherein the control unit is configured to detect a zero cross point based on the detection signal.

In the meantime, the power supply system disclosed in the specification can be applied to an image forming apparatus having an image forming unit that forms an image.

According to the present disclosure, it is possible to provide a technology of more saving power while maintaining detection reliability of a zero cross point.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 is a block diagram showing an electrical configuration of a multifunction apparatus according to a first exemplified embodiment.

FIG. 2 is a circuit diagram of a power supply device (showing a switching power supply-side).

FIG. 3 is a circuit diagram of the power supply device (showing a small capacity power supply circuit, a signal generation circuit, an electric double-layer capacitor, a control device and the like).

FIG. 4 shows a relation of an alternating current voltage of an alternating current power supply and a pulse signal of the signal generation circuit.

FIG. 5 shows output timing of the pulse signal after power is input.

FIG. 6 shows a discharge path of a capacitor.

FIG. 7 is a circuit diagram (a small capacity power supply circuit, a signal generation circuit, an electric double-layer capacitor, a control device and the like) of the power supply device according to a second embodiment.

FIG. 8 is a circuit diagram showing another exemplified embodiment of the power supply device.

DESCRIPTION OF EXEMPLARY EMBODIMENTS First Exemplified Embodiment

A first exemplified embodiment of the present disclosure will be described with reference to FIGS. 1 to 6.

1. Multifunction Apparatus

FIG. 1 is a block diagram showing an electrical configuration of a multifunction apparatus (an example of the image forming apparatus) 1. The multifunction apparatus 1 includes a printing unit 2, a data communication unit 3 that is connected in communication with an information terminal apparatus 7, a FAX communication unit 4 that is connected in communication with a FAX device 8, an image memory 5, a display unit 6 and a power supply system S. The power supply system S is configured by a power supply device 10 and a control device 100. The power supply device 10 is a power supply of the multifunction apparatus 1 and feeds power to the printing unit 2, the data communication unit 3, the FAX communication unit 4, the image memory 5, the display unit 6 and the control device 100. In the meantime, the printing unit 2 is an example of the image forming unit.

The printing unit 2 includes a photosensitive drum 2 a, a charger 2 b that executes a charging process of charging a surface of the photosensitive drum 2 a, an exposure device 2 c that executes an exposure process of forming an electrostatic latent image on the surface of the photosensitive drum 2 a, a developing device 2 d that executes a developing process of attaching developer to the electrostatic latent image formed on the surface of the photosensitive drum 2 a to thus form a developer image, a transfer device 2 e that executes a transfer process of transferring the developer image to a recording medium, a fixing device 2 f that executes a fixing process of fixing the developer image transferred onto the recording medium, and the like.

The printing unit 2 executes the charging process, the exposure process, the developing process, the transfer process and the fixing process, thereby executing printing processing of printing print data or FAX data on the recording medium. The data communication unit 3 performs data communication with the information terminal apparatus 7 such as a PC and receives a printing instruction and print data from the information terminal apparatus 7. The FAX communication unit 4 performs FAX communication with the FAX device 8 and receives FAX data from the FAX device 8. The image memory 5 temporarily stores therein the print data or FAX data received from the information terminal apparatus 7 or FAX device 8.

When the data communication unit 3 receives a printing instruction from the information terminal apparatus 7 to thus receive print data and when the FAX communication unit 4 receives FAX data, the control device 100 of the multifunction apparatus 1 enables the printing unit 2 to execute the printing processing consisting of the charging process, the exposure process, the developing process, the transfer process and the fixing process, thereby printing the print data or FAX data on the recording medium. In the meantime, while an operating voltage of the printing unit 2 is 24V, operating voltages of the data communication unit 3, the FAX communication unit 4, the image memory 5, the display unit 6 and the control device 100 are 3.3V.

2. Circuits of Power Supply System

A configuration of the power supply system S is described with reference to FIGS. 2 and 3. The power supply device 10 includes a switching power supply 20, a small capacity power supply circuit 40 which supply power to the control device when the switching power supply is stopped (specifically, when the control IC 30 stops an on-off control of the FET 25), an electric double-layer capacitor C6 serving as an electricity storage unit, a signal generation circuit 60, a diode D8 for backflow regulation, and the like.

FIG. 2 is a circuit diagram showing a configuration of the switching power supply 20 of the power supply device 10 of the power supply system S. The switching power supply 20 includes a rectification smoothing circuit 21, a transformer 23, a FET (field effect transistor) 25, a rectification smoothing circuit 27, a voltage detection circuit 29 and a control IC 30 that switching-controls the FET 25 and has a function of converting an alternating current (AC) voltage from an AC power supply 15 to a predetermined direct current (DC) voltage and outputting the same.

The rectification smoothing circuit 21 is a so-called capacitor input type and includes a bridge diode D1 that rectifies the AC voltage of the AC power supply 15 and a capacitor C1 that smoothes the rectified voltage. An output-side of the rectification smoothing circuit 21 is provided with the transformer 23, so that an input voltage Vin, which is obtained by rectifying and smoothing the AC voltage, is applied to a primary coil N1 of the transformer 23.

The FET 25 is an N-channel MOSFET and has a drain D that is connected to the primary coil N1 and a source S that is connected to a reference potential of the primary-side. An on-off signal (PWM signal) is applied from an output port OUT of the control IC 30 to a gate G, so that the FET 25 becomes on and off with a predetermined period. Thereby, the primary-side of the transformer 23 oscillates, so that a voltage is induced to a secondary coil N2 of the transformer 23.

The primary-side of the transformer 23 is provided with a voltage generation circuit 31. The voltage generation circuit 31 rectifies and smoothes a voltage, which is induced to an auxiliary coil N3 provided to the primary-side of the transformer 23, by a diode D2 and a capacitor C2. The voltage generation circuit 31 becomes a power supply (about 20V) of the control IC 30.

The rectification smoothing circuit 27 is provided at the secondary-side of the transformer 23 and is configured by a diode D3 and a capacitor C3. The rectification smoothing circuit 27 rectifies and smoothes the voltage induced to the secondary coil N2 of the transformer 23. Thereby, the switching power supply 20 outputs a voltage of DC 24V through an output line Lo1.

As shown in FIG. 2, the output line Lo1 is branched into three lines at a branch point J1, and the branched lines are provided with DC-DC converters 35, 37, respectively. The DC-DC converter 35 drops the output voltage 24V of the switching power supply 20 to 5V and outputs the same from an output line Lo2. The DC-DC converter 37 drops the output voltage 24V of the switching power supply 20 to 3.3V and outputs the same from an output line Lo3. Like this, the switching power supply 20 is configured to output the three voltages of 24V/5V/3.3V.

The voltage detection circuit 29 is provided between the rectification smoothing circuit 27 and the branch point J1 of the output line. The voltage detection circuit 29 is to detect a level of the output voltage Vol (DC 24V) of the switching power supply 20 and is configured by a pair of detection resistances R1, R2, a shunt regulator Re and a light emitting diode LED1 that is connected in series with the shunt regular Re.

The detection resistances R1, R2 are provided between the output line Lo1 and a reference potential GND of the secondary-side and detect a divided voltage Vg that is obtained by dividing the output voltage Vo1 by a resistance ratio. The shunt regulator Re enables current to flow, which corresponds to a level difference between a reference voltage in the shunt regulator Re and the divided voltage Vg. Thereby, the current flows through the light emitting diode LED 1 and the light emitting diode LED 1 outputs a light signal having a light quantity corresponding to the level difference between the reference voltage and the divided voltage Vg.

The light emitting diode LED1 configures a photo coupler together with a photo transistor PT1 connected to a feedback port FB of the control IC 30. For this reason, the light signal of the light emitting diode LED 1 is returned as an electric signal by the photo transistor PT1. Thereby, a signal (hereinafter, referred to as a feedback signal), which indicates the level difference of the divided voltage Vg relative to the reference voltage of the shunt regulator Re, is input (feedback) to the feedback port FB of the control IC 30.

As shown in FIG. 2, the control IC 30 includes a power supply port VCC that is connected to the voltage generation circuit 31, a high voltage input port VH that is connected to a power supply line through a resistance, the feedback port FB to which the feedback signal is input, an output port OUT that outputs an on-off signal (PWM signal) and an EN port to which a mode switching signal Sr (refer to FIG. 3) is input.

The control IC 30 includes a PWM comparator (not shown) and an oscillation circuit (not shown) that oscillates a triangular wave. When the feedback signal is input to the feedback port FB, the control IC 30 generates a PWM signal corresponding to the feedback signal and outputs the same to the gate G of the FET 25 through the output port OUT. Thereby, the output voltage (DC 24V) of the switching power supply 20 is controlled to be a target voltage. Additionally, the control IC 30 has a function of stopping and resuming the switching control (on-off control) of the FET 25, in response to the mode switching signal Sr that is output from the control device 100, which will be described later. In the below descriptions, a non-grounded side power supply line of a pair of power supply lines connected to the AC power supply 15 is referred to as a live LV-side and a grounded-side power supply line is referred to as a neutral NT-side.

The control device 100 has a main block B1 and a mode control block B2. The respective blocks B1, B2 may be configured by one or more CPUs, a hardware circuit such as an ASIC and the like or a combination of a CPU and a hardware circuit. In this exemplary embodiment, the respective blocks B1, B2 have memories 105, 85 embedded therein, respectively.

A power supply port P1 of the main block B1 is connected to the output line Lo3 (refer to FIG. 2) of the DC-DC converter 37 and is fed with the power from the switching power supply 20 through the DC-DC converter 37. The main block B1 controls the entire complex machine 1 including the printing unit 2 and has a function of executing the printing processing of printing the FAX data and print data.

The mode control block B2 has a function of switching an operating mode of the switching power supply 20 between an output mode and a power saving mode. Specifically, in the above exemplary embodiment, the panel switch SW for instructing the switching of the operating mode is provided for the display unit 6. The panel switch SW has one end that is connected to a power supply line L3 and the other end that is connected to an input port P4 provided to the mode control block B2. The other end is connected to the reference potential GND through a resistance. For this reason, when the user operates a panel switch SW2, a voltage of the input port P4 is switched from a low level to a high level. In the meantime, the mode control block B2 is provided with a control port P3. The control port P3 is connected to a base of a transistor Q1 through a resistance to which a capacitor is connected in parallel. The transistor Q1 configure a switching circuit 90 for switching an operating mode of the switching power supply 20, together with a light emitting diode LED2.

The transistor Q1 has an emitter that is connected to the reference potential GND and a collector that is connected to a cathode of the light emitting diode LED2. The light emitting diode LED2 has an anode that is connected to the power supply line L3. The light emitting diode LED2 configures the photo coupler together with a photo transistor PT2 (refer to FIG. 2). A resistance is connected between a base and the emitter of the transistor Q1.

When the user operates the panel switch SW, the mode control block B2 outputs the mode switching signal Sr from the control port P3, in response to the switching of the voltage of the input port P4. When the mode switching signal Sr is output, the transistor Q1 becomes on, so that the light emitting diode LED2 turns on and outputs a light signal. The light signal (the mode switching signal Sr) of the light emitting diode LED2 is returned as an electric signal by the photo transistor PT2 and is input to the EN port of the control IC 30. Then, the control IC 30 stops and resumes the switching control (on-off control) of the FET 25, in response to the input of the mode switching signal Sr, so that the operating mode of the switching power supply 20 is switched between the output mode and the power saving mode.

In the meantime, the output mode is a mode where the control IC 30 executes the switching control to thus switch the switching power supply 20 to the output state. In the output mode, the complex machine 1 can immediately execute the printing processing or the complex machine 1 is executing the printing processing, in response to the printing instruction. Meanwhile, in the power supply system S, when the power supply is input (a power supply plug is connected to the AC power supply 15), the control IC 30 starts the switching control to thus shift the switching power supply 20 to the output mode. The power saving mode is a mode where the switching control of the control IC 30 is stopped to stop the output of the switching power supply 20. In the power saving mode, the main block B1 of the control device 100 is disconnected as regards the power feeding from the switching power supply 20 and is thus stopped. In the meantime, the mode control block B2 is fed with the power from the small capacity power supply circuit 40 and is thus operated, which will be subsequently described.

The small capacity power supply circuit 40 is connected in parallel with the switching power supply 20 with respect to the AC power supply 15. In the power saving mode where the switching power supply 20 is stopped, the small capacity power supply circuit 40 feeds the power to the mode control block B2 of the control device 100. Specifically, as shown in FIG. 3, the small capacity power supply circuit 40 has a first capacitor C4, a second capacitor C5 and a bridge-type rectification circuit 51.

The first capacitor C4 has a first electrode C4p1 and a second electrode C4p2. The first electrode C4p1 is connected to the live LV-side of the AC power supply 15 and the second electrode C4p2 is connected to the rectification circuit 51. The second capacitor C5 has a first electrode C5p1 and a second electrode C5p2. The first electrode C5p1 is connected to the neutral NT-side of the AC power supply 15 and the second electrode C5p2 is connected to the rectification circuit 51. The first capacitor C4 and the second capacitor C5 have high impedances, which are alternating current resistances, and perform a function of making a capacity of the small capacity power supply circuit 40 small, specifically, limiting output current of the rectification circuit 51 to about dozens to hundreds of μA. In the meantime, the capacities of the first capacitor C4 and the second capacitor C5 are 3,300 pF (picofarad), for example.

The rectification circuit 51 is electrically connected between the second electrode C4p2 of the first capacitor C4 and the second electrode C5p2 of the second capacitor C5, thereby rectifying an AC voltage Vac that is applied to both the capacitors C4, C5. The rectification circuit 51 is configured by a bridge circuit consisting of four diodes D4, D5, D6, D7, for example. Cathodes of the diode D4 and the diode D5 are connected at a first connection point Nd1, an anode of the diode D4 is connected to the second electrode C4p2 of the first capacitor C4 and an anode of the diode D5 is connected to the second electrode C5p2 of the second capacitor C5.

Anodes of the diode D6 and the diode D7 are connected at a second connection point Nd2, a cathode of the diode D6 is connected to the second electrode C4p2 of the first capacitor C4 and a cathode of the diode D7 is connected to the second electrode C5p2 of the second capacitor C5.

An output line L2 of the rectification circuit 51 joins an output line (5V power output line Lo2) of the switching power supply 20 at a common connection point J2. A power supply line L3 having joined the two output lines L2, Lo2 is connected to the power supply port P2 of the mode control block B2. Thereby, the power can be fed to the mode control block B2 from any of the switching power supply 20 and the small capacity power supply circuit 40. That is, in the output mode where the switching power supply 20 is at the output state, the power is fed to the mode control block B2 from the switching power supply 20 or small capacity power supply circuit 40. In the power saving mode where the output of the switching power supply 20 is stopped, the power is fed from the small capacity power supply circuit 40 to the mode control block B2.

An electric double-layer capacitor C6 serving as the electricity storage unit is provided at a downstream side close to the mode control block B2, when seen from the common connection point J2. The electric double-layer capacitor C6 is provided between the power supply line L3 and the reference potential GND. In the power saving mode where the output of the switching power supply 20 is stopped, the electric double-layer capacitor C6 functions as a power supply driving the light emitting diode LED2 of the switching circuit 90, and functions as a backup power supply for feeding the power to an RTC (which is a circuit measuring current time and is used to detect FAX reception time) 80 provided for the mode control block B2 upon the disconnection of the AC power supply 15. Meanwhile, the RTC is an abbreviation of ‘real-time clock’.

The signal generation circuit 60 is connected to the output line L2 of the rectification circuit 51. The signal generation circuit 60 is a circuit that generates a pulse signal Sp corresponding to an AC voltage Vac of the AC power supply 15, and includes a resistance R3, a transistor Q2, a resistance R4, a zener diode ZD1 and a reverse voltage applying circuit 70.

The transistor Q2 is an NPN transistor and has an emitter that is connected to the reference potential GND and a collector connected to the output line L2 through a resistance R4. The transistor Q2 has a base that is connected to a connection point of the zener diode ZD1 and the resistance R3. The resistance R3 has one end that is connected to the base of the transistor Q2 and the other end that is connected to the emitter of the transistor Q2. The zener diode ZD1 has an anode that is connected to the base of the transistor Q2 and a cathode that is connected to the output line L2.

A part of current Ip (current shown by chain line FIG. 3) that is output from the rectification circuit 51 towards the signal generation circuit 60 flows to the base of the transistor Q2 through the zener diode ZD1 or capacitor C7.

As shown in FIG. 4, during a period (a period K1 in FIG. 4) for which the current Ip which flows from the rectification circuit 51 towards the signal generation circuit 60 is higher than a reference value X, a voltage between the base and emitter of the transistor Q2 exceeds a threshold voltage and the current flowing through the base becomes a predetermined threshold value or larger, so that the transistor Q2 becomes on. During a period (a period K2 in FIG. 4) for which the current is lower than the reference value X, the current flowing through the base becomes smaller than the predetermined threshold value, so that the transistor Q2 becomes off. Since the rectification circuit 51 rectifies the output of the AC power supply 15, the output of the signal generation circuit 60, i.e., the output (a potential of the collector) of the transistor Q2 becomes the pulse signal Sp corresponding to the AC voltage Vac of the AC power supply 15. In this example, the pulse signal is a pulse signal having the same period as the AC voltage Vac and becomes a signal having a phase that is offset with respect to the AC voltage Vac. In the meantime, the transistor Q2 is an example of the ‘switching device’ and the pulse signal Sp is an example of the ‘detection signal’.

An output line of the signal generation circuit 60 (an output line drawn out from the collector of the transistor Q2) is connected to an input port P5 of the mode control block B2 of the control device 100 and the pulse signal Sp output from the signal generation circuit 60 is input to the mode control block B2. For this reason, the input pulse signal Sp is data-processed in the main block B1 or mode control block B2 of the control device 100, so that a zero cross point Zp of the AC voltage Vac of the AC power supply 15 can be detected.

Specifically, as shown in FIG. 4, a phase of the current Ip flowing through the resistance R3 progresses by 90° with respect to the AC voltage Vac of the AC power supply 15. Therefore, the zero cross point ZP of the AC voltage Vac coincides with a center of the period (the period of a low level) K1 during which the pulse signal Sp is not output or a center of the period (the period of a high level) K2 during which the pulse signal Sp is output. Hence, it is possible to detect the zero cross point Zp of the AC voltage Vac of the AC power supply 15 by detecting the center of the period K1 during which the signal is not output and the center of the period K2 during which the signal is output.

For example, a zero cross point ZP1 shown in FIG. 4 can be obtained by a following equation 1.

t4=t3+(K1/2)  (equation 1)

time t4 is occurrence time of the zero cross point ZP1 and time t3 is ascending time of the pulse signal Sp.

A zero cross point ZP2 shown in FIG. 4 can be obtained by a following equation 1.

t6=t5+(K2/2)  (equation 2)

time t6 is occurrence time of the zero cross point ZP2 and time t5 is ascending time of the pulse signal Sp.

In the meantime, the reason to detect the zero cross point ZP of the AC power supply 15 by using the pulse signal Sp output from the signal generation circuit 60 is because the control device 100 controls the printing unit 2 by using the detection of the zero cross point ZP. Specifically, the control device 100 performs control of an energization amount (firing angle control or wave number control) on a heater 2 h (see FIG. 1) configuring the fixing device 2 f, based on the zero cross point ZP of the AC power supply 15. A signal Szc shown in FIG. 4 is a zero cross signal that is generated in the control device 100 from a detection result of the zero cross point ZP. The zero cross signal Szc is used to detect timing of the zero cross point ZP when performing the control of an energization amount of the heater 2 h. In addition to this, it is possible to detect whether a power supply plug Y is connected to the AC power supply 15, depending on whether or not the zero cross signal Szc.

The zener diode ZD1 has a function of limiting a voltage V2 of the output line L2 of the rectification circuit 51 to a voltage lower than a voltage V3 of the power supply line L3. That is, the voltage V3 of the power supply line L3 is a voltage that is obtained by subtracting a voltage drop of the forward diode D9 from 5V, which is a line voltage of the output line Lo2 of the switching power supply 20. Since the voltage drop of the forward diode D9 is slight and may be regarded as zero, the voltage V3 of the power supply line L3 is about 5V.

In the meantime, the voltage V2 of the output line L2 of the rectification circuit 51 is a voltage that is obtained by adding a zener voltage (a breakdown voltage) of the zener diode ZD1 to the base voltage of the transistor Q2. In the power supply system S of this exemplary embodiment, the zener voltage of the zener diode ZD1 is set to be 3.9V. The base voltage of the transistor Q2 is about 0.6V. For this reason, the voltage V2 of the output line L2 of the rectification circuit 51 is limited to 4.5V or lower. That is, a peak is cut at 4.5V. In this way, the voltage V2 of the output line L2 of the rectification circuit 51 is set to be a voltage lower than the voltage V3 of the power supply line L3, so that it is possible to increase responsiveness of the signal generation circuit 60 upon the input of the power supply.

The reason is described as follows. When the power supply plug Y (refer to FIG. 2) is connected to the AC power supply 15, the switching power supply 20 is activated and is thus at the output state and the small capacity power supply circuit 40 is also at the output state. When the power supply plug Y is connected at a state where the electric double-layer capacitor C6 is not charged, the charging current flows towards the electric double-layer capacitor C6 through the power supply line L3.

If the voltage V2 of the output line L2 of the rectification circuit 51 is higher than the voltage V3 of the power supply line L3 (V2>V3), the charging current flows not only from the switching power supply 20 towards the electric double-layer capacitor C6 but also from the rectification circuit 51 of the small capacity power supply circuit 40 towards the electric double-layer capacitor C6.

For this reason, the current little flows through the resistance R3 or transistor Q2 of the signal generation circuit 60 until the electric double-layer capacitor C6 is completely charged. Hence, since the transistor Q2 is kept at the off state until the charging is completed, the pulse signal Sp is not output from the signal generation circuit 60 and it is substantially impossible to detect the zero cross point ZP of the AC power supply 15.

Regarding the above problem, in the power supply system S of this exemplary embodiment, the voltage V2 of the output line L2 of the rectification circuit 51 is set to be lower than the voltage V3 of the power supply line L3 (V2<V3). When the voltage V2 of the output line L2 of the rectification circuit 51 is set to be lower than the voltage V3 of the power supply line L3, the output current of the rectification circuit 51 does not flow towards the power supply line L3 but flows towards the signal generation circuit 60 while the switching power supply 20 is being activated.

Therefore, when the switching power supply 20 is activated as the power supply plug Y is connected, the output current of the rectification circuit 51 mostly flows towards the signal generation circuit 60 along a dashed-dotted line shown in FIG. 3, irrespective of whether the electric double-layer capacitor C6 is not charged. As a result, since the signal generation circuit 60 outputs the pulse signal Sp just after the power supply plug Y is connected, it is possible to detect the zero cross point ZP of the AC power supply 15 just after the power supply plug Y is connected (in an example of FIG. 5, about 0.1 s).

When the voltage V2 of the output line L2 of the rectification circuit 51 is set to be lower than the voltage V3 of the power supply line L3, the current may flow back from the switching power supply 20 towards rectification circuit 51 during the output of the switching power supply 20, so that the transistor Q2 may be kept at the on state. Regarding this, in the power supply system S of this exemplary embodiment, a diode D8 for backflow regulation is provided on the output line L2 of the rectification circuit 51. Therefore, it is possible to regulate the backflow of the current from the switching power supply 20 towards the rectification circuit 51 by the diode D8. In addition to the diode, a transistor or FET may be adopted as the backflow regulation element. However, since the diode is cheaper than the other elements, it has a cost merit.

In the power supply system S of this exemplified embodiment, the signal generation circuit 60 is provided with the reverse voltage applying circuit 70. The reverse voltage applying circuit 70 includes a capacitor C7, a first discharge resistance R5 and a second discharge resistance R3. The capacitor C7 is provided between the base of the transistor Q2 and the output line L2 of the rectification circuit 51. The first discharge resistance R5 is connected between the output line L2 of the rectification circuit 51 and the reference potential GND. The second discharge resistance R3 is connected between the emitter and base of the transistor Q2.

The capacitor C7 is charged by the current Ip flowing to the signal generating circuit 60 through the path shown by the chain line of FIG. 3. The capacitor C7 is discharged when the current Ip does not flow. As shown with a dashed-dotted line in FIG. 6, the discharge current of the capacitor C7 flows through a path of the first discharge resistance R5 and the second discharge resistance R3. For this reason, as shown in FIG. 4, during the off-period of the transistor Q2, a voltage of the base (the control terminal) becomes negative by an operation of the discharge current of the capacitor C7. Hence, the on-off operations of the transistor Q2 become stable, without malfunction of the transistor Q2 caused due to noises. Therefore, since it is possible to detect a signal having a stable pulse, as the pulse signal Sp, it is possible to improve the detection precision of the zero cross point ZP. In the meantime, a period hatched in FIG. 4 indicates a discharge cycle of the capacitor C7 and the voltage of the base of the transistor Q2 becomes negative during the period.

3. Effects

The output current (the rectified current) of the rectification circuit 51 configuring the small capacity power supply circuit 40 is significantly smaller by the operations of the first capacitor C4 and the second capacitor C5, compared to the output current (the rectified current) of the bridge diode D1 of the rectification smoothing circuit 21 configuring the switching power supply 20. For this reason, it is possible to detect the zero cross point ZP without using the photo coupler, by performing the zero cross detection method using the output current of the rectification circuit 51 configuring the small capacity power supply circuit 40. Therefore, compared to the zero cross detection method using the photo coupler, since it is not necessary to drive the photo diode so as to detect the zero cross point, it is possible to suppress the power consumption, thereby saving the power. Since the output of the rectification circuit 51 rectifies the AC output of the AC power supply 15, it is possible to maintain the detection reliability of the zero cross point ZP by detecting the zero cross point ZP based on the output of the rectification circuit 51.

In the power supply system S of this exemplary embodiment, the voltage V2 of the output line L2 of the rectification circuit 51 is set to be lower than the voltage V3 of the power supply line L3 (V2<V3). For this reason, the signal generation circuit 60 can output the pulse signal Sp just after the power supply is input, and it is possible to detect the zero cross point ZP of the AC power supply 15 just after the power supply is input.

In particular, since an apparatus having the FAX function such as the complex machine 1 should record reception time of the FAX data, it is preferable to provide the RTC circuit 80 measuring the current time. However, since the apparatus having the RTC circuit 80 embedded therein should operate the RTC circuit 80 even at a state where the power supply is cut off, the capacity of the electricity storage unit (in this example, the electric double-layer capacitor C6) becomes larger. For this reason, it takes to charge the electricity storage unit after the power supply is input and the signal generation circuit 60 does not substantially operate during the charging period, so that it takes to make a state where it is possible to detect the zero cross point ZP of the AC power supply 15. When the power supply system S according to the exemplary embodiment is applied to the complex machine 1, it is possible to considerably reduce the time after the power supply is input until the zero cross point ZP of the AC power supply 15 can be detected, which is very effective, compared to a configuration where the power supply system of the related art is mounted.

Second Exemplary Embodiment

In the below, a second exemplary embodiment is described with reference to FIG. 7.

In the second exemplary embodiment, the configuration of the circuit of the power supply system S of the first exemplary embodiment is partially changed. The same configurations as the first exemplary embodiment are denoted with the same reference numerals and the descriptions thereof are omitted. The differences with the first exemplary embodiment are described.

The circuit of the first exemplary embodiment has a problem in that when the output of the switching power supply 20 is stopped, the voltage of the electric double-layer capacitor C6 is gradually dropped from 5V and is finally lowered to 4.5V, which is the voltage of the output line L2 of the rectification circuit 51.

Hence, in the power supply system S of the second exemplary embodiment, as shown in FIG. 7, a 24V output line Lo1 of the switching power supply 20 is connected to the power supply line L3. For this reason, from a standpoint of a voltage balance, when the voltage V2 of the output line L2 of the rectification circuit 51 is suppressed to at least 24V or lower, it is possible to maintain the relation of V2<V3. Thus, like the first exemplary embodiment, the signal generation circuit 60 can output the pulse signal Sp just after the power supply is input, and it is possible to detect the zero cross point ZP of the AC power supply 15 just after the power supply is input.

Therefore, in the power supply system S of the second exemplary embodiment, the zener voltage of the zener diode ZD1 included in the signal generation circuit 60 is set to be about 5.1V and the voltage V2 of the output line L2 of the rectification circuit 51 is set to be a voltage (in this example, 5.7V) higher than 5V, which is a charge target voltage of the electric double-layer capacitor. Therefore, even when the switching power supply 20 stops the output, it is possible to maintain the voltage of the electric double-layer capacitor C6 at 5V that is a charge target voltage.

By the above configuration, compared to the power supply system S of the first exemplary embodiment, even when the switching power supply 20 is at a stop, it is possible to securely drive the light emitting diode LED2 and to positively switch the operating mode of the switching power supply 20. When the same charging amount is secured, a voltage drop is smaller, so that the power supply system S of the second exemplary embodiment can make the capacity of the electric double-layer capacitor C6 smaller.

The power supply system S of the second exemplary embodiment has a zener diode ZD2 that is provided between the power supply line L3 and the reference potential GND. A zener voltage of the zener diode ZD2 is about 5V and a voltage of a more downstream side of the power supply line L3 than the zener diode ZD2 can be limited to about 5V. In this way, the input voltage to the mode control block B2 can be suppressed to be a withstand voltage or lower.

A resistance R6 is provided on the power supply line L3 between the connection point J2 of the output line L1 and a connection point J3 of the zener diode ZD2. The resistance R6 has a function of limiting the current flowing from the switching power supply 20 towards the zener diode ZD2 through the output line Lo1. In this way, the resistance R6 is provided to thus limit the current, so that the power consumption of the switching power supply 20 can be suppressed.

In the power supply system S of the second exemplary embodiment, a dedicated charging path L4 for the electric double-layer capacitor C6 is provided. The charging path L4 connects the 5V power output line Lo2 of the switching power supply 20 to the electric double-layer capacitor C6 through a forward diode D10. Since the charging path L4 has an impedance that is set to be lower than the charging path passing through the power supply line L3 (the high resistance R6 or resistance R7 is not provided, so that an impedance is lower), it is possible to charge the electric double-layer capacitor C6 in a short time.

Other Exemplary Embodiments

The invention is not limited to the above exemplary embodiments shown in the drawings and following exemplary embodiments are also included in the technical scope of the invention.

(1) In the first and second exemplary embodiments, the power supply system S is applied to the complex machine 1. However, the power supply system S can be applied to any electric device and the utility of the power supply system S is not limited to the complex machine 1. For example, the power supply system S can be widely applied to home appliances such as a television, a video recorder and the like. In the first and second exemplary embodiments, although the electrophotographic configuration has been exemplified as an example of the printing unit, an inkjet configuration is also possible.

(2) In the first and second exemplary embodiments, the signal generation circuit 60 is provided with the reverse voltage applying circuit 70. However, the reverse voltage applying circuit 70 is not necessarily required. That is, as shown in FIG. 8, the capacitor C7 and the first discharge resistance R5 may be omitted. In the first exemplary embodiment, the resistance R4 of the signal generation circuit 60 is connected to the anode of the diode D8. However, the resistance R4 may be connected to the cathode of the diode D8.

(3) In the first and second exemplary embodiments, the diode D8 has been exemplified as the backflow regulation element. However, a transistor or FET may be also used.

(4) In the first and second exemplary embodiments, the electric double-layer capacitor C6 has been exemplified as an example of the electricity storage unit. However, any element may be used inasmuch as it can store the electricity, and a secondary battery and the like may be also used. Also, an electrolytic capacitor may be used. 

What is claimed:
 1. A power supply system comprising: a switching power supply configured to rectify and smooth an alternating current voltage of an alternating current power supply and generate a predetermined direct current voltage; a first capacitor including a first electrode and a second electrode, the first electrode being connected to one end of the alternating current power supply; a second capacitor including a third electrode and a fourth electrode, the third electrode being connected to the other end of the alternating current power supply; a rectification circuit configured to rectify an alternating current voltage applied to the first and second capacitors, the rectification circuit including an output line connected with an output line of the switching power supply; a backflow regulation element that is provided on the output line of the rectification circuit and is configured to regulate backflow of current from the switching power supply towards the rectification circuit; a signal generation circuit connected to the output line of the rectification circuit, the signal generation circuit configured to generate a detection signal corresponding to a zero cross point of the alternating current power supply based on an output of the rectification circuit; a power supply line positioned at a more downstream side than the backflow regulation element and connected to the output line of the switching power supply and the output line of the rectification circuit; an electricity storage unit connected to the power supply line; a voltage limit element configured to limit a voltage of the output line of the rectification circuit to be lower than a voltage of the power supply line, and a control unit that is positioned at a more downstream side than the electricity storage unit, power being fed to the control unit through the power supply line, wherein the control unit is configured to detect a zero cross point based on the detection signal.
 2. The power supply system according to claim 1, wherein the backflow regulation element is a diode.
 3. The power supply system according to claim 1, wherein the signal generation circuit includes a switching device configured to be turned on and off based on the output of the rectification circuit and generate the detection signal corresponding to the zero cross point of the alternating current power supply.
 4. The power supply system according to claim 3 further comprising a reverse voltage applying circuit configured to turn off the switching device by applying, to a control terminal of the switching device, a voltage having a reverse polarity to a voltage turning on the switching device.
 5. The power supply system according to claim 4, wherein the switching device is a transistor having an emitter connected to a reference potential-side and a collector connected to the output line of the rectification circuit, and the reverse voltage applying circuit includes: a capacitor provided between a base of the transistor and the output line of the rectification circuit, a first discharge resistance connected between the output line of the rectification circuit and the reference potential, and a second discharge resistance connected between the emitter and base of the transistor.
 6. The power supply system according to claim 1, wherein the electricity storage unit includes a dedicated charging path having impedance lower than a charging path passing through the power supply line.
 7. The power supply system according to claim 6, further comprising: a constant voltage element configured to make a voltage of the power supply line be a constant voltage that is a voltage lower than the output voltage of the switching power supply; and a current limit element that is provided on the power supply line and is configured to limit current flowing from the switching power supply towards the constant voltage element.
 8. The power supply system according to claim 1, further comprising a switching circuit configured to switch an output state where the switching power supply generates the direct current voltage and a stop state where the switching power supply stops an output, wherein the electricity storage unit stores electricity by output current of the rectification circuit or output current of the switching power supply, and wherein the stored electricity becomes power for the switching circuit.
 9. An image forming apparatus comprising: a power supply system comprising: a switching power supply configured to rectify and smooth an alternating current voltage of an alternating current power supply and generate a predetermined direct current voltage; a first capacitor including a first electrode and a second electrode, the first electrode being connected to one end of the alternating current power supply; a second capacitor including a third electrode and a fourth electrode, the third electrode being connected to the other end of the alternating current power supply; a rectification circuit configured to rectify an alternating current voltage applied to the first and second capacitors, the rectification circuit including an output line connected with an output line of the switching power supply; a backflow regulation element that is provided on the output line of the rectification circuit and is configured to regulate backflow of current from the switching power supply towards the rectification circuit; a signal generation circuit connected to the output line of the rectification circuit, the signal generation circuit configured to generate a detection signal corresponding to a zero cross point of the alternating current power supply based on an output of the rectification circuit; a power supply line positioned at a more downstream side than the backflow regulation element and connected to the output line of the switching power supply and the output line of the rectification circuit; an electricity storage unit connected to the power supply line; a voltage limit element configured to limit a voltage of the output line of the rectification circuit to be lower than a voltage of the power supply line, and a control unit that is positioned at a more downstream side than the electricity storage unit, power being fed to the control unit through the power supply line; and an image forming unit that forms an image, wherein the control unit is configured to detect a zero cross point based on the detection signal, and control the image forming unit by using the detection of the zero cross point.
 10. The image forming apparatus according to claim 9, wherein the image forming apparatus includes a communication unit transmitting and receiving FAX data and having a FAX function, and the control unit includes an RTC circuit configured to measure current time. 